While the integration degree is improved and the semiconductor devices and wirings in a semiconductor integrated circuit are made fine, the number of multi-layer wiring layers is increasing still more. It is desired to reduce the resistance of a fine wiring so as to guarantee a high speed operation in the wiring. In place of aluminum, copper having a lower resistance is used. A copper wiring forming process has a limit, if this process forms a copper wiring by finely pattering a copper layer through photolithography.
In order to form a fine copper wiring, a damascene process has been adopted. A wiring trench and/or via hole is formed in an insulating layer, the trench and/or via hole is buried with a copper wiring layer, and an unnecessary copper wiring layer on the insulating layer is removed by chemical mechanical polishing (CMP) or the like. The damascene process includes a single damascene process and a dual damascene process.
With the single damascene process, a via hole is formed through a lower level insulating layer and buried with a copper wiring layer, and an unnecessary portion is removed by CMP. Next, an upper level insulating layer is formed, a wiring trench is formed and buried with a copper wiring layer, and an unnecessary portion is removed by CMP. With the dual damascene process, an insulating layer is formed, a recess having a wiring trench and a via hole is formed thorough the insulating layer and buried with a copper wiring layer, and an unnecessary portion is removed by CMP.
Copper has the properties that it is diffused into an insulating layer and the insulating characteristics of the insulating layer are degraded. Therefore, when a copper wiring is formed by the damascene process, a barrier metal layer having a copper diffusion preventing function is formed, and then a copper layer is formed on the barrier metal layer. Used as barrier metal are nitride such as titanium nitride TiN and tantalum nitride TaN, tantalum Ta and the like.
A copper layer is exposed on the surface of a copper wiring after CMP. In order to prevent copper from diffusing from this copper layer to an upper level insulating layer, the surface of the copper wiring is covered with an insulating copper diffusion preventing layer. This copper diffusion preventing layer has also an etch stopper function when the upper level insulating layer is etched. The insulating copper diffusion preventing layer is usually made of silicon nitride SiN, silicon carbide SiC or the like.
There is the proposal that after a copper wiring with a lower level barrier metal layer is formed, the surface of a wiring layer is etched and dug, and an upper level barrier metal layer is formed and an unnecessary portion is removed by CMP (Patent Document 1). The structure has been proposed which has a recess in an upper level barrier layer in which an aluminum layer is buried (Patent Document 2).
It is desired to reduce an effective dielectric constant of an insulating layer surrounding a wiring so as to guarantee a high speed operation in the wiring. Although an etch stopper and copper diffusion preventing film is made of SiN or SiC, other insulating layers are preferably made of material having a low dielectric constant in order to reduce parasitic capacitance of wirings. Insulating materials having a dielectric constant lower than that of silicon oxide have the properties specific to each material. A multi-layer wiring structure is desired to be formed by considering the properties of each insulating material.
Patent Document 1:
Japanese Patent Laid-open Publication No. HEI-6-275612
Patent Document 2:
Japanese Patent Laid-open Publication No. 2001-110809